Efficient determination of feedback DAC errors for digital correction in ΔΣ A/D converters

Feedback DAC errors in a ∆Σ analog to digital converter are determined by measuring the idle channel output and removing the DAC elements one by one. This method requires simple computation, does not add excess loop delay, and requires no reconfiguration of the ∆Σ modulator. The errors so determined can be used to correct the output codes in the digital domain or the DAC elements in the analog domain. This technique is a useful alternative to the popular dynamic element matching at high speeds as excess delay cannot be tolerated and at low oversampling ratios where DEM can result in tones. Simulation results indicate that the correction values can be obtained to an accuracy that is sufficient to reduce noise and distortion to nearly ideal levels. I. MOTIVATION Multibit ∆Σ A/D converters are capable of a significantly higher in-band signal to quantization noise ratio (SQNR) compared to their single bit counterparts because they have an inherently smaller quantization step and they permit higher out of band gains[1]. They are also less prone to idle channel tones[1]. The single biggest drawback of multibit modulators is the nonlinearity of the feedback DAC which increases distortion and quantization noise in the signal band. Dynamic element matching (DEM) is an effective and popular technique to convert the distortion into shaped noise and significantly improve the in band performance. However, this requires multiple stages of gates or switches in the digital feedback path-e.g. data weighted averaging (DWA) for a 4 bit DAC requires a four stage barrel shifter driven from the accumulated input. Higher order dynamic element matching schemes require more complex computations. For high speed modulators the delay introduced by the DEM logic can be a significant fraction of the sampling period and is best avoided.